1. Field of the Invention
The invention relates to an etching method in an integrated circuit (IC), and more particularly to a method of etching the cap silicon nitride layer (Cap-SiN) on a poly-silicon gate or a mask silicon nitride layer for fabricating a shallow trench isolation (STI), so that the bias of the critical dimension (CD) is improved.
2. Description of the Related Art
Referring to FIG. 1, a conventional poly-silicon gate is shown. On a semiconductor substrate 100, a poly-gate comprises a gate oxide layer 101, a poly-silicon layer 102, a metal silicide layer 103, for example, a tungsten silicide (WSi) due to the very poor conductivity of poly-silicon, and a cap silicon nitride layer 104. The cap silicon nitride layer 104 is formed to prevent the damage of the poly-gate in the subsequent process, for example, damage caused during the formation of a source/drain region or self-aligned window, In addition, with the formation of the cap silicon nitride layer, the necking effect caused by subsequent exposure process during photolithography is prevented. In a conventional process of patterning the silicon nitride layer, a silicon nitride layer is formed first. Using a photo-mask, a photo-resist layer is formed on the silicon nitride layer. The exposed silicon nitride layer is then removed by anisotropic plasma etching. In the conventional method, fluoro-methane polymer (CF.sub.x) are in use, for example, tri-fluoro-methane (CHF.sub.3)/tetra-fluoro-methane (CF.sub.4)/argon(Ar). The flow rate of the tri-fluoro-methane and the tetra-fluoro-methane are about 30 sccm to 70 sccm, and the flow rate of the argon is about 400 sccm to 800 sccm. Since the particle of fluoro-methane polymer is very large, the etched surface is very rough and ragged. Therefore, a large CD bias is produced. In the subsequent process, for example, in the subsequent photo-lithography, a serious misalignment or an error during exposure is easily caused due to a large CD bias, so that the device reliability is decreased, and the production quality is degraded.
On the other hand, while forming a shallow trench isolation, a similar problem occurs. Referring to FIG. 2a, on a semiconductor substrate 200, a mask silicon nitride layer 201 is formed. A photo-resist layer 202 is formed on the mask silicon nitride layer 201. Using photo-lithography and etching, the photo-resist layer 202 is defined as shown as 202a in FIG. 2a.
Referring to FIG. 2b, using anisotropic plasma etching, the exposed silicon nitride layer 201. In the conventional method, fluoro-methane polymer (CF.sub.x) are in use, for example, tri-fluoro-methane (CHF.sub.3)/tetra-fluoro-methane (CF.sub.4)/argon(Ar). The flow rate of the tri-fluoro-methane and the tetra-fluoro-methane are about 30 sccm to 70 sccm, and the flow rate of the argon is about 400 sccm to 800 sccm. Since the particle of fluoro-methane polymer is very large, the etched surface is very rough and ragged. Therefore, a large CD bias is produced. The resultant silicon nitride layer 201a is shown as figure. In addition, during etching, a fluoride layer is formed. The formation of the fluoride cause the difficulty of forming a gate oxide layer in the subsequent process. Using a conventional method, a part of the semiconductor substrate 200 is removed, so that a trench is formed within the substrate 200. By filling the trench with an insulated material, for example, an oxide, an shallow trench isolation is formed.